연구홍보포털

논문 초록 (Abstract)

The growing demand for high-performance computing and compact electronics has driven the transition toward advanced three-dimensional (3D) packaging technologies. Traditional packaging technologies, such as micro-bump interconnections, face limitations in achieving sub-micrometer pitches, prompting the development of alternative bonding strategies. Among them, Cu/SiO2 hybrid bonding (HB) has emerged as a promising method for enabling fine-pitch, high-density interconnects in next-generation semiconductor packaging. In this study, a reliable low-temperature Cu/SiO2 HB process was developed by combining metal electroless deposition (ELD) on sub-micron pitch Cu pads with selective surface functionalization of the SiO2 dielectric layer using silane. The ELD process facilitated uniform and selective Au deposition on Cu, acting as a diffusion metal that maintained interfacial stability during bonding. Conclusively, the SiO2 surface was modified with (3-aminopropyl)triethoxysilane (APTES), which formed strong covalent networks through silane polymerization, enhancing adhesion at the dielectric interface. This dual modification strategy facilitated direct Cu–Cu bonding and robust SiO2–SiO2 adhesion, resulting in a defect-free interface without voids or delamination. The bonding was conducted at a low-temperature of 250 ∘ C, thereby minimizing thermal stress typically associated with conventional high-temperature bonding processes. These result clearly demonstrates a practical and scalable method for achieving low-temperature Cu/SiO2 HB, contributing to the advancement of 3D integration in semiconductor packaging.