논문 해외 국제전문학술지(SCI급) Vertically Integrated Multiple Nanowire Field Effect Transistor
- 학술지 구분 국제전문학술지(SCI급)
- 게재년월 2015-11
- 저자명 Byung-Hyun Lee, Min-Ho Kang, Dae-Chul Ahn, Jun-Young Park, Tewook Bang, Seung-Bae Jeon,Jae Hur, Dongil Lee and Yang-Kyu Choi
- 학술지명 Nano letters
- 발행처명 ACS Publications
- 발행국가 해외
- 논문언어 외국어
홈페이지논문 초록 (Abstract)
A vertically integrated multiple channel-based field-effect transistor (FET) with the highest number of nanowires reported ever is demonstrated on a bulk silicon substrate without use of wet etching. The driving current is increased by 5-fold due to the inherent vertically stacked five-level nanowires, thus showing good feasibility of three-dimensional integration-based high performance transistor. The developed fabrication process, which is simple and reproducible, is used to create multiple stiction-free and uniformly sized nanowires with the aid of the one-route all-dry etching process (ORADEP). Furthermore, the proposed FET is revamped to create nonvolatile memory with the adoption of a charge trapping layer for enhanced practicality. Thus, this research suggests an ultimate design for the end-of-the-roadmap devices to overcome the limits of scaling.