연구홍보포털

논문 초록 (Abstract)

Micro-electronic devices are increasingly incorporating miniature multi-layered integrated architectures. However, the localization of faults in three-dimensional structure remains challenging. This study involved the experimental and numerical estimation of the depth of a thermally active heating source buried in multi-layered silicon wafer architecture by using both phase information from an infrared microscopy and finite element simulation. Infrared images were acquired and real-time processed by a lock-in method. It is well known that the lock-in method can increasingly improve detection performance by enhancing the spatial and thermal resolution of measurements. Operational principle of the lock-in method is discussed, and it is represented that phase shift of the thermal emission from a silicon wafer stacked heat source chip (SSHSC) specimen can provide good metrics for the depth of the heat source buried in SSHSCs. Depth was also estimated by analyzing the transient thermal responses using the coupled electro-thermal simulations. Furthermore, the effects of the volumetric heat source configuration mimicking the 3D through silicon via integration package were investigated. Both the infrared microscopic imaging with the lock-in method and FE simulation were potentially useful for 3D isolation of exothermic faults and their depth estimation for multi-layered structures, especially in packaged semiconductors.